1 ps8500 10/02/00 product pin configuration logic block diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2502a product description the pi6c2502a features a low-skew, low-jitter, phase-locked loop (pll) clock driver. by connecting the feedback fb_out output to the feedback fb_in input, the propagation delay from the clk_in input to any clock output will be nearly zero. product features high-performance phase-locked-loop clock distribution for networking, synchronous dram modules for server/workstation/ pc applications allows clock input to have spread spectrum modulation for emi reduction zero input-to-output delay low jitter: cycle-to-cycle jitter 75ps max. on-chip series damping resistor at clock output drivers for low noise and emi reduction operates at 3.3v v cc wide range of clock frequencies 80 to 134 mhz package: plastic 8-pin soic package (w) 8-pin w phase-locked loop clock driver application if a system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as pi6c2509q, and pi6c2510q, is likely to be impractical. the device-to-device skew introduced can significantly reduce the performance. pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. as shown in figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. for example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. figure 1. this combination provides zero-delay between the reference clocks signal and 17 outputs. clk_in fb_in pll av cc fb_out clk_out 1 2 3 v cc 4 clk_out clk_in gnd fb_in 8 7 6 5 agnd fb_out av cc 17 zero delay buffer pi6c2502 reference clock signal clk_out feedback 18 output non-zero delay buffer v
pi6c2502a phase-locked loop clock driver 2 ps8500 10/02/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 e m a n n i pr e b m u n n i pe p y tn o i t p i r c s e d n i _ k l c8i . t u p n i k c o l c e c n e r e f e rn i _ k l c. t u p n i k c o l c m u r t c e p s d a e r p s s w o l l a n i _ b f5i . t u p n i k c a b d e e fn i _ b f. l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f e h t s e d i v o r p t u o _ b f2o t u p t u o k c a b d e e ft u o _ b f. k c a b d e e f l a n r e t x e r o f d e t a c i d e d s i e u l a v e m a s e h t f o r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h t u o _ b f s t u p t u o k c o l c e h t s a. t u o _ k l c t u o _ k l c3o f o s e i p o c w e k s - w o l e d i v o r p s t u p t u o e s e h t . s t u p t u o k c o l c. n i _ k l c . r o t s i s e r g n i p m a d - s e i r e s d e d d e b m e n a s a h t u p t u o h c a e v a c c 7r e w o p v a . y l p p u s r e w o p g o l a n a c c r o f l l p e h t s s a p y b o t d e s u o s l a e b n a c v a n e h w . s e s o p r u p t s e t c c d e s s a p y b s i l l p , d n u o r g o t d e p p a r t s s i d n an i _ k l c. s t u p t u o e c i v e d e h t o t y l t c e r i d d e r e f f u b s i d n g a1 d n u o r g . y r t i u c r i c g o l a n a e h t r o f e c n e r e f e r d n u o r g e h t s e d i v o r p d n g a . d n u o r g g o l a n a v c c 4r e w o p. y l p p u s r e w o p d n g6 d n u o r g. d n u o r g pin functions l o b m y sr e t e m a r a p. n i m. x a ms t i n u v i e g n a r e g a t l o v t u p n i 5 . 0 ? v c c 5 . 0 + v v o e g n a r e g a t l o v t u p t u o v c d _ i e g a t l o v t u p n i c d 8 . 3 i c d _ o t n e r r u c t u p t u o c d 0 0 1a m r e w o pt t a n o i t a p i s s i d r e w o p m u m i x a m a 5 5 = o r i a l l i t s n i c0 . 1w t g t s e r u t a r e p m e t e g a r o t s5 6 ?0 5 1 o c dc specifications (absolute maximum ratings over operating free-air temperature range) r e t e m a r a ps n o i t i d n o c t s e tv c c . n i m. p y t. x a ms t i n u i c c v i v = c c i ; d n g r o o 0 = ) 1 ( t n e r r u c y b d n a t sv 6 . 30 1 m a c i v i v = c c d n g r o v 3 . 3 4 f p c o v o v = c c d n g r o6 note: stress beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. note: 1. continuous output current
3 ps8500 10/02/00 pi6c2502a phase-locked loop clock driver 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 l o b m y sr e t e m a r a p. n i m. x a ms t i n u f k l c a 2 0 5 2 c 6 i p y c n e u q e r f k c o l c0 84 3 1z h m d i y c e l c y c y t u d k c o l c t u p n i0 40 6% p u r e w o p r e t f a e m i t n o i t a z i l i b a t s 1s m ac specifications (timing requirements over recommended ranges of supply voltage and operating free-air temperature) r e t e m a r a p) t u p n i ( m o r f) t u p t u o ( o t v c c c 0 7 - 0 , v 3 . 0 v 3 . 3 = s t i n u . n i m. p y t. x a m r e t t i j t u o h t i w r o r r e e s a h p tn i _ k l c - z h m 6 6 & 0 0 1 t an i _ b f - 0 5 1 ?0 5 1 + s p e l c y c - o t - e l c y c , r e t t i jz h m 6 6 & 0 0 1 t a t u o _ k l c 5 7 ?5 7 + e l c y c y t u d 5 45 5% v 0 . 2 o t v 4 . 0 , e m i t - e s i r , r t 0 . 1 s n v 4 . 0 o t v 0 . 2 , e m i t - l l a f , f t 1 . 1 switching characteristics (over recommended ranges of supply voltage and operating free-air temperature, cl = 30pf) note: these switching parameters are guaranteed by design. electrical characteristics (over recommended operating free-air temperature range pull up/down currents of pi6c2502a, v cc = 3.0v) l o b m y sr e t e m a r a pn o i t i d n o c. n i m. x a ms t i n u i h o t n e r r u c p u - l l u pv 4 . 2 = t u o v6 . 3 1 ? a m t n e r r u c p u - l l u pv 0 . 2 = t u o v2 2 ? i l o t n e r r u c n w o d - l l u pv 8 . 0 = t u o v9 1 t n e r r u c n w o d - l l u pv 5 5 . 0 = t u o v3 1 recommended operating conditions l o b m y sr e t e m a r a p. n i m. x a ms t i n u v c c e g a t l o v y l p p u s0 . 36 . 3 v v h i e g a t l o v t u p n i l e v e l h g i h0 . 2 v l i e g a t l o v t u p n i l e v e l w o l8 . 0 v i e g a t l o v t u p n i0v c c t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o00 7c o
pi6c2502a phase-locked loop clock driver 4 ps8500 10/02/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com package mechanical information plastic 8-pin soic package e d o c g n i r e d r oe m a n e g a k c a pe p y t e g a k c a pe g n a r g n i t a r e p o w a 2 0 5 2 c 6 i p8 wc i o s l i m - 0 5 1 n i p - 8l a i c r e m m o c ordering information .0040 .0098 seating plane .013 .020 .050 bsc .016 .0075 .0098 1 8 .0099 .0196 0-8? .050 .149 .157 x.xx x.xx denotes dimensions in millimeters 3.78 3.99 .189 .196 4.80 5.00 1.27 .016 .026 1.35 1.75 .2284 .2440 5.80 6.20 0.406 0.660 0.330 0.508 0.10 0.25 0.40 1.27 0.19 0.25 0.25 0.50 x 45? .053 .068 ref
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